1. Field of the Invention
The present invention relates to semiconductor devices and the manufacturing methods thereof and, in particular, to an area-saving accommodation of a semiconductor device in a package and to a semiconductor device which may be deposited onto a circuit board, for example by means of solder, in an area-saving way, wherein the present invention may particularly be applied to a novel standardized model for discrete elements such as, for example, diodes, transistors, switches and filters, but also to more complex integrated circuit assemblies.
2. Description of Related Art
The forms of packages presently used for single semiconductor elements or semiconductor devices may generally be divided into two groups, namely wired package types and package types having solder bumps. According to the first group of package forms for semiconductor devices above indicated, discrete semiconductor devices are presently mainly produced and offered in so-called SMD packages (SMD=surface mounted device). With this form of package, a semiconductor chip is applied or mounted to a metallic support (lead) or lead frame, wherein so-called bond wires (connecting wires) connect the contact pads (semiconductor contacts) of the semiconductor chip to the metallic support or lead frame. Thus, supports or lead frames in the application are connected to the associated conductive traces on the circuit board by means of solder in an electrically and/or thermally conducting way. The backside contact of the semiconductor chip here may also form an electrical and/or thermal contact to the lead frame. After connecting the semiconductor chip to the lead frame, the system is potted and thus closed by a sealing mass (mould). The metallic supports here are all on one side of the resulting package (such as, for example, TSLP models) or are led out from the package or the sealing mass laterally in a flat or bended manner (such as, for example, TSFP and SOT models).
The second group of models for semiconductor device packages are so-called WLP device packages (WLP=wafer level package) or CSP device packages (CSP=chip size package). In this second group of package forms, metallic solder bumps are deposited onto the pads or contacts of the semiconductor chip and subsequently provided with a semiconductor passivation, i.e. an insulation or protective material. Semiconductor devices of this kind having a WLP or CSP package are then connected to the conductive traces or contact pads to the conductive traces of the application boards by means of a flip chip process such that the solder bumps then make electrical contact in the application from the semiconductor device to the conductive traces of the circuit board.
Regarding these WLP and CSP package forms for semiconductor devices, reference is, for example, made to a manufacturing process flow for producing a shell BGA package form by Shellcase-Wafer Level Packaging, which is, for example, published over the following internet link (http://www.xintec.com.tw/product/ShellBGA_Process_Flow_New %200422′04.pdf).
It should be kept in mind with the above-mentioned manufacturing process of “Shellcase” that in the manufacturing methods for WLP package forms having BGA structures (BGA=ball grid array) illustrated, metallic connections are provided between the contact pads of a semiconductor chip and the solder bumps on the top face of the semiconductor device to allow re-wiring of the connecting lines in this way.
Regarding the solder bumps for WLP and CSP package forms described above, it should generally be kept in mind that, caused by manufacturing and the requirements of the mounting process on the application board, they have a minimum size and a minimum distance to one another, which has the result that the resulting semiconductor chip, i.e. the semiconductor chip accommodated in a WLP or CSP package, must be considerably larger than the active area of the semiconductor device, such as, for example, the active area of a diode or a transistor.
It has been observed from the above explanations that an essential problem of conventional package models for semiconductor devices is that the resulting total size of the semiconductor device accommodated in the package is considerably larger than the active area on the semiconductor chip, wherein this becomes particularly evident in small-signal transistors and diodes where the contact pads and the unused areas therebetween which remain empty due to the minimum distance of the contact areas account for a considerable portion of the total device area. High-frequency diodes or high-frequency transistors and the semiconductor chips thereof, for example, have lengths and widths in the order of magnitude of 0.2 mm to 0.4 mm and a height of about 0.1 mm. When these semiconductor chips are accommodated in the wired packages mentioned above, the smallest package forms available at present comprise dimensions in the order of magnitude of half a millimeter (0.5 mm) per side length.
In order to obtain these dimensions in the order of magnitude indicated, the height of a conventional semiconductor chip is particularly reduced to a value of 0.1 mm in order to achieve a final resulting height of less than half a millimeter, including the bond wires required and the sealing mass. Additionally, it should be kept in mind that the solder bumps used in CSP and WLP package forms have a diameter in the order of magnitude of 0.4 mm so that relatively large chip dimensions are required for the single semiconductor device.
Regarding the package designs or package forms for semiconductor devices known from the prior art, problems result in that these package forms require a considerably larger area than the dimensions of the active regions of the single semiconductor would require. Furthermore, the standardized models for semiconductor devices discussed above comprise a relatively large height due to the accommodation in a package, this being extremely critical dimensions in particular in modules consisting of a plurality of semiconductor devices. Additionally, it should be noted that assembling the semiconductor chip (i.e. accommodating the single semiconductor chips in a package), which is to a great extent determined by material costs, is frequently the most expensive part of manufacturing the single semiconductor product.
Regarding the assembling costs for semiconductor devices, it should also be kept in mind that, with a present 6-inch semiconductor wafer for example, there are about 100,000 to 200,000 single elements on the semiconductor wafer so that accommodating the diced semiconductor chip in one of the package forms described above in single chip processes in semiconductor device manufacturing is a very complicated and thus expensive matter.
Also, it should be noted with regard to the WLP and CSP package forms discussed above that they operate with metallic solder bumps which, however, show quality deficiencies with temperature cycling and generally only have a very poor thermal conductivity. These solder bumps can only provide a limited thermal contact so that problems of semiconductor devices having these packages forms, particularly with regard to temperature cycling resistance, frequently cannot be avoided.
This results from CSP or WLP semiconductor devices to be connected to the circuit board via the metallic bumps such that thermal differences between the semiconductor device and the circuit board may only be compensated via the solder connections. Because the solder bumps, however, have a relatively poor thermal conductivity, this may, when operating the semiconductor device which is thermally heated due to the dissipation, result in a temperature difference between the circuit board and the semiconductor device, which is frequently compensated for via the metallic solder bumps in a relatively insufficient way. This may also result in mechanical tension between the circuit board and the semiconductor device such that the quality deficiencies may result with regard to WLP or CSP semiconductor devices with temperature cycling mentioned above.
Regarding the TSLP package forms and the flip chip package forms having bumps known from the prior art, which presently are the smallest models for semiconductor devices, it should be kept in mind that after building these semiconductor devices into the application, the electrical contacts of these semiconductor devices can no longer be subjected to an optical inspection after being soldered in the application circuit, since in these package forms the contact (solder contact) with the conductive traces of the application circuit is covered by the package and the semiconductor device.